W25Q64FVSFIG【PDF 49/89 页】IC SPI FLASH 64MBIT 16SOIC

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W25Q64FV

6.2.24

64KB Block Erase (D8h)

The Block Erase instruction sets all memory within a specified block (64K-bytes) to the erased state of all

1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase

Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low

and shifting the instruction code “D8h” followed a 24 -bit block address (A23-A0). The Block Erase

instruction sequence is shown in Figure 23a & 23b.

The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done

the Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block Erase

instruction will commence for a time duration of t BE (See AC Characteristics). While the Block Erase cycle

is in progress, the Read Status Register instruction may still be accessed for checking the status of the

BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished

and the device is ready to accept other instructions again. After the Block Erase cycle has finished the

Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase instruction will not be

executed if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0)

bits (see Status Register Memory Protection table).

/CS

Mode 3

0

1

2

3

4

5

6

7

8

9

29

30

31

Mode 3

CLK

Mode 0

Instruction (D8h)

24-Bit Address

Mode 0

DI

(IO 0 )

23

*

22

2

1

0

DO

(IO 1 )

* = MSB

/CS

High Impedance

Figure 23a. 64KB Block Erase Instruction (SPI Mode)

Mode 3

0

1

2

3

4

5

6

7

Mode 3

CLK

Mode 0

Mode 0

In structio n

D8h

A23-16

A15-8

A7-0

IO 0

IO 1

IO 2

IO 3

20

21

22

23

16

17

18

19

12

13

14

15

8

9

10

11

4

5

6

7

0

1

2

3

Figure 23b. 64KB Block Erase Instruction (QPI Mode)

- 49 -

Publication Release Date:

October 07, 2013

Revision L

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